Field
The disclosed technology generally relates to semiconductor devices, and more particularly to transistor devices comprising multiple channels, and associated complementary metal-oxide-semiconductor (CMOS) devices.
Description of the Related Technology
Moore's Law predicts a roadmap for scaling semiconductor devices in CMOS technology. In order to be able to further scale CMOS devices in the future, silicon CMOS technology is being complemented or replaced by technology based on other material systems.
Gate-all-around devices, e.g., gate-all-around transistors, comprising channel regions formed of nanowires and gates that completely surround the channel regions, have been recognized as devices that can improve various device parameters, e.g., the short channel control, at advanced nodes in order to allow continued scaling of critical dimensions, e.g., gate length.
Moreover, in order to maintain or improve drive current per chip area in a predetermined gate region having limited foot print with continued scaling, process architectures in which multiple nanowires are vertically stacked relative to one another have been proposed.
Another trend in CMOS processing, is to combine different semiconductor materials as channel materials on the same substrate, for instance, for use as NMOS and PMOS devices.
In US 2013/0270512 A1 NMOS and PMOS nanowire devices are disclosed wherein both NMOS and PMOS devices comprise a vertical stack of nanowires to achieve a greater current carrying capability (e.g. larger drive currents) for a given device footprint over a substrate. The NMOS nanowire transistor comprises group III-V semiconductor material, e.g. GaAs, while the PMOS nanowire comprises group IV semiconductor material, e.g. Germanium. In some embodiments, both NMOS and PMOS device fabrication comprises the growth of a single stack of layers wherein alternatingly a layer of a group IV semiconductor material and a layer of a group III-V semiconductor material are grown on top of each other. In an NMOS region, the group IV semiconductor layer is then selectively removed, while in a PMOS region the group III-V semiconductor layer is selectively removed.
There is a need in industry to provide alternative solutions which allow the combination of more than two different semiconductor materials as channel materials on the same substrate.